In radio frequency (RF) circuit design, nano-scale multi-finger (MF) MOSFETs are widely used since use of the multi-finger structure may effectively reduce gate resistance by changing the finger width and the finger number (i.e., number of fingers) of the gate fingers, thereby achieving a higher maximum oscillation frequency and lower noise at high frequency.
With miniaturization of the devices to nano-scale dimensions, the source/drain extension (SDE) region may introduce significant impact on some important device parameters, such as electrical integrity, subthreshold leakage current, overlap capacitance, etc. An ultra-shallow junction (USJ) of the SDE region may effectively suppress the short channel effects (SCE), but may increase the resistance of the SDE region and degrade the driving current. In addition, a length of an overlapping region between the gate and the SDE region (LSDE) is an important parameter to be known accurately because an effective channel length (Lch) is obtained by subtracting the length of the overlapping region (LSDE) from the gate length (Lg). In case that the gate length (Lg) is fixed, a longer length of the overlapping region (LSDE) may lead to a shorter effective channel length (Lch) and thus a larger leakage current from the source to the drain.
A conventional method for extracting the gate length (Lg) and the length of the overlapping region (LSDE) is to provide two test pieces on which semiconductor devices (e.g., MOSFETs) with the same layout dimension are disposed, to use a scanning electron microscope (SEM) to measure gate lengths of the semiconductor devices on one of the test pieces, and to perform electrical measurement on the semiconductor devices on the other one of the test pieces, thereby determining the length of the overlapping region (LSDE). However, the semiconductor devices on different test pieces might not have the same gate length even with the same layout dimension due to process variation, which may become more prominent with miniaturization of the devices, causing excessive differences among nano-scale devices. Moreover, the destructive SEM measurement is time-consuming and generates extra material cost while the reproducibility of measurement cannot be ensured. Furthermore, in conventional parameter extraction methods, two-dimensional conditions are usually considered, while three-dimensional effects, such as poly finger-end fringing capacitance, may be overlooked. Such conventional methods are inapplicable to the multi-finger gate devices.
In order to enhance the precision of electrical analysis and simulation for the semiconductor devices, especially the nano-scale devices, it is a goal in relevant industry to precisely extract the length of the overlapping region (LSDE) and the effective channel length (Lch) of the multi-finger gate devices.